Automotive engine controllers use microprocessor based electronics for monitoring all the appropriate engine and transmission operating parameters and providing the control signals necessary to optimize the vehicle performance. A host microprocessor control unit (MCU) such as a Motorola MC6800 or MC68000 processor is the primary control but special calculations are often handled by a secondary programmable chip to furnish information to the MCU. Here it is proposed to provide a secondary IC called a timer I/O or TIO co-processor which handles all the input and output functions for the control as well as to execute algorithms which relieve the MCU of some burdens.
It is desired that the TIO control external processes using time-based algorithms with a minimum of host overhead. The major goals of this IC are: programmability, resolution, throughput, and reduction of host MCU overhead. The inputs to the TIO include signals from the vehicle speed sensor, crankshaft and camshaft position sensors, mass air flow sensors, transmission gear sensor and others. The time between the occurrence of an event (a change in the signal) and the TIO's awareness of the event is the resolution. A high resolution is needed for accurate and timely processing. Throughput, which also should be high, is the speed at which events can be recognized, processed and acted upon. Programmability refers to the ease with which the function of the IC can be changed to execute new algorithms. Algorithms handled by the co-processor include calculations for spark timing, fuel injection, mass air flow input, stepper motor control, transmission control and vehicle speed sensor.
The timer operations can be seen as two distinctly different types of programs: complex algorithms of variable length and simple timing functions having high resolution. It is proposed to provide a processor arrangement for running both types of programs simultaneously so that the timing functions can be carried out with a high degree of accuracy and not degraded by compromise with the other programs. A number of ways to accomplish this goal are apparent but generally they involve hardware duplication and thus high expense, as well as difficult programming.
The U.S. Pat. No. 4,244,028 to Haines discloses a time shared adder controlled by interleaved clock pulses such that during one pulse instructions are fetched and during the next pulse the instructions are executed by the adder. During the fetching operation the adder is free to perform another function and according to the patent the hardware as arranged to use the adder to increment a register. There is no provision for simultaneously running two or more programs.
The U.S. Pat. No. 4,320,453 Roberts et al discloses a dual sequencer microprocessor utilizing a pipeline configuration and an address processing circuit having two sets of input lines and one set of output lines providing interleaved microinstructions for simultaneously controlling two real-time tasks.
A technique for running two or more programs concurrently without extensive hardware or programming penalties is reported in a pair of companion papers by Lee and Messerschmitt, "Pipeline Interleaved Programmable DSP's: Architecture," IEEE Trans. Acoust., Speech, Signal Processing, Vol. ASSP-35, p.1320, September, 1987, and "Pipeline Interleaved Programmable DSP's: Synchronous Data Flow Programming," IEEE Trans. Acoust., Speech, Signal Processing, Vol. ASSP-35, p.1334, September, 1987, which are incorporated herein by reference. According to these papers, a processor can simulate a plurality of machines by interleaving programs for the several machines and, if a pipelined configuration is used with the pipeline stages equal to the number of machines, a high processor utilization will be achieved and programming difficulties will be avoided.
We recognize that when the processor is used as two or more machines, each machine can be dedicated to a peculiar type of operation not affected by the functions of another machine. By applying the interleaved pipeline technique to the particular objective of the engine controller, one can achieve the execution of fairly complex algorithms of various running times and at the same time to regularly and frequently check the state of each input pin to obtain the high resolution. By providing a two stage pipeline and by interleaving the instructions of two different programs, a processor may be made to appear as two separate virtual machines running programs simultaneously and independently, although they share the same memory and execution unit. Then a program or a number of programs having complex algorithms can be run on one machine while the timing program can be run, without interruption, on the other machine.